2. Instruction Register *

3. Scan Check Circuit *

4. JTAG Data Registers *

4.1. Configuring a pixel column *

4.2. Configuring a global register *

4.3. Bypass and Scan_Check Registers *

4.4. Boundary Scan Register *

5. Appendix *

1. Introduction

These notes are written as a guide to configuring the chip via the JTAG serial interface. They contain listings of the codes necessary to operate the JTAG controller and address the internal registers. The majority of the JTAG interface circuitry on the chip complies with the IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 1149.1), and we assume that the reader is familiar with this standard.

In the chip, the following convention has been adopted:

the LSB of a register is the bit which is shifted-out first during the shift sequence; ie it is the contents of the flip-flop nearest to the TDO port.

In compliance with standard, the JTAG block on the chip consists of a controller, instruction register, boundary scan register, bypass register and data registers. In addition, there is a block to carry out a simple check of the functionality of the previous chip in the serial chain (scan check sequence). This is for the ALICE scenario and is described in Section 3.

The input/output signals are TMS, TCLK, TRESET*, TDI0, TDI1 and TDO. TMS, TCLK and TRESET* comply with the standard. In the ALICE scenario, TDI0 is an input which is taken from the TDO of the previous chip (n-1) in the serial chain and TDI1 is taken from the chip before that (n-2). The selection of which input to use is done during the scan check sequence. In the LHCb scenario, these two pins should be connected together.

 

2. Instruction Register

The instruction register is compliant with IEEE 1149.1. It is a 4-bit register whose value after reset is 1111, which selects the bypass mode. Note that the capture value of the instruction register is fixed to be 1101. The data shifted into the instruction register define what action is to be carried out by the JTAG circuitry. The instruction set is listed in the following table:

Instruction	Code (msb…..lsb)
Sel_EXTEST	0000
Sel_ENBL	0001
Sel_THR	0010
Sel_TM	0011
Sel_GLOBAL	0100
Sel_SP (sample/preload)	0101
Sel_SCAN_CHECK	0110
Sel_BYPASS	1111

The data registers which are selected by these instructions are described in Section 4.

3. Scan Check Circuit

The scan check block is the only feature which is not part of the IEEE 1149.1 standard.

In the ALICE scenario, the scan check sequence is carried out after execution of the TEST_LOGIC_RESET state of the TAP controller. It is not used in the LHCb scenario, where data should be loaded through TDI0. The sequence consists of shifting the capture value of the instruction register in each chip (n-1) into the instruction register of the next chip in the chain (n). This requires that the TAP controller execute the states CAPTURE_IR, SHIFT_IR and UPDATE_IR. The value loaded into the instruction register by the UPDATE_IR command is compared with the expected value of 1101. A negative comparison signifies an error in the functionality of chip n-1. A multiplexer selects between TDI0 and TDI1 according to the result of this comparison, and ensures that the JTAG chain is complete. Immediately after a TEST_LOGIC_RESET state, TDI0 is selected by default. Note that the selection of the TDI0 or TDI1 is determined by the value loaded into the instruction register by the first UPDATE_IR executed after leaving the TEST_LOGIC_RESET state. This selection will remain until another TEST_LOGIC_RESET state has been executed. The result of the comparison is also latched by the scan-check register, as described in Section 4.

 

4. JTAG Data Registers

Notes:

1. Each pixel contains five configuration bits(TEST, MASK,THRESHOLD ADJUST BITS 0,1,2) and one flip-flop which is in the JTAG register chain. After shifting in data to this flip-flop, its contents are transferred to one of the five configuration bits. This bit is pre-selected as explained below. The state of these bits after reset is 0. The capture value of a pixel column register is the stored values of the selected bits of that column.
2. The enable register contents are used to address the pixel columns and the global registers. Its state after reset is 0000000. The capture value is 00000000.
3. The global registers contain the digital settings of the on-chip DACs (42 registers), the setting of the on-chip delay (1 register), and a special register which contains a strobe delay control and leakage current compensation control. (See below and the list of registers in the appendix). The state of the global registers after reset is 10000000. The capture value is the stored value of the register.
4. The bypass register is according to the JTAG standard, and is selected after a reset or when the chip is in bypass mode. Its state after reset is 0. The capture value is 0.
5. The scan-check register is used to store the result of the scan-check sequence (ALICE only). Its state after reset is 0 (which selects TDI0). The capture value is the result of the scan check (0 selects TDI0, 1 selects TDI1).
6. The boundary-scan register is according to the JTAG standard, and allows access to the I/O pins of the chip. The cells go to 0 on reset. The capture value is the logic value applied to the pad.

The loading of these registers is explained in the subsequent sections.

1. Configuring a pixel column

The loading of configuration data into a column of pixels is a two-step process.

1. Selecting the column and the configuration bit to load: the column address and a code to select the configuration bit must be loaded into the enable register. To load the enable register, it should be selected by the SEL_ENBL instruction. The corresponding contents of the 7-bit enable register are shown in the following table:

Msb						lsb
BIT_1	BIT_0	A4	A3	A2	A1	A0

Bits A0-4 select the column address (0 – 31). BIT_1 and BIT_0 select the configuration bit according to the following settings:

BIT_1	BIT_0	SELECTED
0	0	No selection
0	1	THRESH B0 or TEST
1	0	THRESH B1 or MASK
1	1	THRESH B2

2. Shifting the data into the column: To load this data, either the sel_THR or sel_TM instructions should be executed. 256 bits of data are then shifted into the shift register of the selected column. At the end of the shift, the contents of the shift register are parallel-loaded into the selected configuration bit in each pixel. Note that the configuration bit to be loaded is selected by choosing the appropriate instruction (sel_THR or sel_TM) AND setting the two bits BIT_1 and BIT_0 accordingly. For example, to load the THRESH B1 bits of column 9, the enable register should be loaded with:

1. Configuring a global register

The loading of the global registers is a two-step process, similar to that for the pixel columns in section 2.

i) Selecting the global register: the address of the global register must be loaded into the enable register. To load the enable register, it should be selected by the sel_ENBL instruction. The corresponding contents of the 7-bit enable register are shown in the following table:

Bits A0-5 select the global address (0-63 of which 0-43 are used). DAC_OUT_EN is used for sensing the outputs of the DAC addressed by A0-5. If DAC_OUT_EN is set high, then the output of the DAC will be connected to one of the output pads DAC_SENSE_I or DAC_SENSE_V (depending on whether the DAC produces a voltage or a current).

2. Shifting the data into the global register: 8 bits of data are then shifted into the flip-flops of the selected global register. To load this data, the sel_GLOBAL instruction should be executed.

The list of global registers and their 6-bit addresses is in the appendix to this note.

1. Bypass and Scan_Check Registers

The Bypass register complies with IEEE standard 1149.1. It is selected by the sel_BYPASS instruction.

The Scan_Check register consists of one bit. When selected, it will capture the result of the scan-check sequence, and can then be shifted out to identify the location of any faults in the serial JTAG chain. It is selected by the sel_SCAN_CHK instruction.

2. Boundary Scan Register

The boundary scan register is a serial chain of cells, each of which is connected to an input or output pin of the chip. This allows the setting of known values on these pins via the JTAG port, and facilitates testing. The register is selected by the sel_SP or sel_EXTEST instruction.

There are 38 elements in the boundary scan register, and these are listed in the following table:

IMPORTANT: The following two points should be noted, and the appropriate actions taken:

1. The values loaded into boundary scan cells for CLK* and CLK (20 and 21) should always be complementary (ie 0 and 1 or 1 and 0).
2. Entry into the sel_EXTEST instruction changes the mode of the output pads from high-impedance to active mode. In the ALICE scenario, it is vital that only one chip at a time is put into sel_EXTEST mode. Otherwise, the output pads of the selected chips will be shorted together via the bus.

1. Appendix