For the standard readout of the chip, the following three control signals are used:

1. NEVR* (next-event-read)
2. CE* (chip enable)
3. CLK and CLK* (continuous system clock)

NB These signals are all inverted logic, GTL levels (logic 1 = 400mV, logic 0 = 1.2V).

NEVR* and CE* should have the same phase with respect to CLK.

NEVR* and CE* are both synchronised to the rising edge of CLK and inverted to CMOS levels (logic 0 = 0V and logic 1 = 1.6V) on the chip. They are renamed as NEVR_synch and CE_synch, as shown in timing diagram A.

The set-up (t_su) and hold (t_hold) times are shown in Table 1.

data waiting in the pixel FIFOs are parallel loaded into the output shift registers (one per column). They are then ready for shifting out.

b) If (CE_synch = 1) AND (NEVR_synch = 0) (ie CE* = 400mV, NEVR* = 1.2V):

data are clocked down the output registers at frequency of the system clock.

CE_synch enables the clock to the output shift registers. NEVR_synch vetoes this clock to allow the loading of the shift register.

The duration of CE* determines how many bits are shifted out. In addition, there is an extra flip flop on each output pad to re-synchronise the data to the clock.

This output data is synchronised to the rising edge of CLK. Also note that there is a delay of one clock period between CE* being asserted and the first data appearing at the output pad. This is due to the re-synchronising flip-flop. There is a further delay due to the propagation delay of the output buffer, represented as t_del and indicated in Table 1.

The presence of the synchronisation flip flop means that an additional clock pulse is required to read out a complete column of pixels.

Thus for ALICE mode (256 pixels per column), CE* should be asserted for 257 clock periods.

For LHCb mode (32 pixels per column), CE* should be asserted for 33 clock periods.

Timing Diagram A illustrates the protocol and the output data for one column of 16 pixels. The output levels are again inverted GTL (logic 1 = 400mV, logic 0 = 1.2V). The output buffer is in the tri-state (high impedance) mode until CE* enables the shifting-out of the data. After the shift is complete, the output state returns to high impedance.

The data shift registers are reset by the shift; logic 0 is shifted down the column following the data. This is shown in Timing Diagram A: after the data from pixel 15 is transferred, the output is logic 0 (1.2V) for half a clock cycle before returning to high impedance.