Please refer to the accompanying timing diagram.

For producing test pulses in the pixels and then triggering the chip to store these pulses, the following control signals are used:

1. STROBE* (strobe = level-0 trigger)
2. TEST_PULSE* (logical test pulse)
3. CLK and CLK* (continuous system clock)

NB These signals are all inverted logic, GTL levels (logic 1 = 400mV, logic 0 = 1.2V).

Note that STROBE* should have a fixed phase with respect to CLK.

STROBE* is re-synchronised to the rising edge of CLK and inverted to CMOS levels (logic 0 = 0V and logic 1 = 1.6V) on the chip.

The set-up time (t_su) is 5ns.

The minimum hold time (t_hold) is one clock period.

IMPORTANT: TEST_PULSE* should NOT be synchronised to the clock. During the testing of the chip, the phase of TEST_PULSE* with respect to the clock will be scanned to determine the optimal timing.

The delay between TEST_PULSE* and STROBE* should match the delay setting on the chip (configurable via JTAG). If the timing is correct, then a logic 1 is loaded into the FIFO of the corresponding pixel.

With the optimal timing, the length of STROBE* is one clock period. However, the chip will operate with STROBE* a few clock periods long. This will be helpful for initial testing and timing adjustments.